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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
32WQ and 64WQ Family with Asynchronous RAM
Datasheet
Product Features

Device Architecture -- Flash Density: 32-Mbit, 64-Mbit -- Async PSRAM Density: 8-, 16-, 32Mbit; Async SRAM Density: 4-, 8-, 16Mbit -- Top, Bottom or Dual flash parameter configuration Device Voltage -- Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V -- RAM VCC = 3.0 V; RAM VCCQ = 1.8 V or 3.0 V Device Packaging -- 88 balls (8 x 10 active ball matrix); Area: 8x10 mm; Height: 1.2 mm to 1.4 mm PSRAM Performance -- 70 ns initial access, 25 ns async page reads at 1.8 V I/O -- 70 ns initial access async PSRAM at 1.8V I/O -- 88 ns initial access, 30 ns async page reads at 1.8 V I/O -- 85 ns initial access, 35 ns async page reads at 3.0 V I/O -- 70 ns initial access, 25 ns async page reads at 3.0 V I/O SRAM Performance -- 70 ns initial access at 1.8 V or 3.0 V I/O

Flash Performance -- 65 ns initial access at 1.8 V I/O -- 70 ns initial access at 3.0 V I/O -- 25 ns async page at 1.8 V or 3.0 V I/O -- 14 ns sync reads (tCHQV) at 1.8 V I/O -- 20 ns sync reads (tCHQV) at 3.0 V I/O -- Enhanced Factory Programming: 3.10 s/Word (Typ) Flash Architecture -- Read-While-Write/Erase -- Asymmetrical blocking structure -- 4-KWord parameter blocks (Top or Bottom); 32-KWord main blocks -- 4-Mbit partition size -- 128-bit One-Time Programmable (OTP) Protection Register -- Zero-latency block locking -- Absolute write protection with block lock using F-VPP and F-WP# Flash Software -- Intel(R) Flash Data Integrator (FDI) and Common Flash Interface (CFI) Quality and Reliability -- Extended Temperature: -25 C to +85 C -- Minimum 100K flash block erase cycle -- 90 nm ETOXTM IX flash technology -- 130 nm ETOXTM VIII flash technology
The Intel(R) Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus static RAM combinations in a common package footprint. The flash memory features 1.8 V lowpower operations with flexible, multi-partition, dual-operation Read-While-Write / Read-WhileErase, asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, one PSRAM die, and one SRAM die in a low-profile package compatible with other SCSP families with QUAD+ ballout.
Order Number: 251407, Revision: 010 www..com 18-Oct-2005
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Le ga l Lin es an d Discla ime rs
Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. All Rights Reserved.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
32WQ and 64WQ Family--Intel(R) Wireless Flash Memory (W18/W30 SCSP)
1.0
Introduction....................................................................................................................................6 1.1 1.2 Nomenclature ....................................................................................................................... 6 Conventions.......................................................................................................................... 6
2.0
Functional Overview .....................................................................................................................8 2.1 2.2 Block Diagram ...................................................................................................................... 8 Flash Memory Map and Partitioning ..................................................................................... 9
3.0 4.0
Package Information ...................................................................................................................11 Ballout and Signal Description ..................................................................................................13 4.1 4.2 Signal Ballout......................................................................................................................13 Signal Descriptions .............................................................................................................14
5.0
Maximum Ratings and Operating Conditions...........................................................................16 5.1 5.2 5.3 Absolute Maximum Ratings ................................................................................................ 16 Operating Conditions .......................................................................................................... 17 Capacitance........................................................................................................................ 17
6.0
Electrical Specifications .............................................................................................................18 6.1 DC Characteristics.............................................................................................................. 18
7.0
AC Characteristics ......................................................................................................................21 7.1 7.2 7.3 7.4 Flash AC Characteristics ....................................................................................................21 SRAM AC Characteristics...................................................................................................21 PSRAM AC Characteristics ................................................................................................ 24 Device AC Test Conditions................................................................................................. 29
8.0 9.0
Flash Power Consumption .........................................................................................................30 Device Operation ......................................................................................................................... 31 9.1 9.2 Bus Operations ...................................................................................................................31 Flash Command Definitions................................................................................................ 34
10.0 Flash Read Operations ............................................................................................................... 35 11.0 Flash Program Operations .........................................................................................................36 12.0 Flash Erase Operations .............................................................................................................. 37 13.0 Flash Security Modes.................................................................................................................. 38 14.0 Flash Read Configuration Register ........................................................................................... 39 15.0 SRAM Operations ........................................................................................................................ 40 15.1 15.2 Power-up Sequence and Initialization ................................................................................ 40 Data Retention Mode.......................................................................................................... 40
16.0 PSRAM Operations......................................................................................................................42 16.1 16.2 16.3 Power-Up Sequence and Initialization................................................................................ 42 16.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).......................................42 Standby Mode/ Deep Power-Down Mode .......................................................................... 43 PSRAM Special Read and Write Constraints .....................................................................43
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)--32WQ and 64WQ Family
Appendix A Write State Machine ........................................................................................................ 45 Appendix B Common Flash Interface................................................................................................. 46 Appendix C Flash Flowcharts .............................................................................................................47 Appendix D Additional Information .................................................................................................... 48 Appendix E Ordering Information ....................................................................................................... 49
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
32WQ and 64WQ Family--Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Revision History
Date June 2003 September 2003 May 2004 Revision -001 -002 -006 Initial release. Changed PSRAM Read values. Added new Transient Equivalent Testing Load Circuit figure. General text edits. Reformatted the datasheet and moved sections around according to the new layout. Added 90 nm product information. Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50. Added DC and AC specs for the new line items and edits to related sections. Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50 Added 32WQ product information. June 2005 October 2005 -009 -010 Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50 Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification Updated Ordering Information Description
August 2004
-007
January 2005
-008
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
1.0
Introduction
This document contains information pertaining to the products in the Intel(R) Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + PSRAM, and flash + SRAM options.This document provides information where this SCSP family differs from the Intel(R) Wireless Flash Memory (W18/W30) discrete device. Refer to the discrete datasheets Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for flash product details not included in this SCSP datasheet.
1.1
Nomenclature
0x 0b Byte CFI CUI DU ETOX FDI k (noun) Kb KB Kword M (noun) Mb MB OTP PLR PR PRD RCR RFU SCSP SR SRD Word WSM Hexadecimal prefix Binary prefix 8 bits Common Flash Interface Command User Interface Don't Use EPROM Tunnel Oxide Flash Data Integrator (Intel(R) software solution) 1 thousand 1024 bits 1024 bytes 1024 words 1 million 1,048,576 bits 1,048,576 bytes One-Time Programmable Protection Lock Register Protection Register Protection Register Data Read Configuration Register Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data 16 bits Write State Machine
1.2
Conventions
Group Membership Brackets: Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1]. VCC vs. VCC: When referring to a signal or package-connection name, the notation used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as VCC, etc.
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Device: This term is used interchangeably throughout this document to denote either a particular die, or the combination of multiple die within a single package. F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chip-enable or output enable at the same time. When each is referred to individually, the reference will be F1CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die #2). F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with "P-" (e.g., P-VCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with "S-" (e.g., S-VCC or S-VCC). P-VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM. R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, R-UB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
2.0
Functional Overview
This section provides an overview of the features and capabilities of the Intel(R) Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device. The W18/W30 SCSP device provides flash + RAM die combinations. Products range from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same package footprint and signal ballout. Table 21 on page 50 lists possible product combinations for the 32-Mbit and 64-Mbit W18/W30 SCSP family.
2.1
Block Diagram
Figure 1 shows all internal package connections for the SCSP family with multiple die. See Table 21 for valid combinations of flash and RAM die. Unused connections on combinations with less than three die are reserved and should not be used. Please contact your local Intel representative for details regarding any reserved or RFU pins.
Figure 1.
Block Diagram
F2-VCC F2-CE# F2-OE#
Flash Die #2 32- or 64-Mbit W18/W30
CLK ADV# F-WP# F-RST#
F-WE# F-VPP VCCQ WAIT
F1-OE# F1-CE# F1-VCC A[MAX:0]
Flash Die #1 32- or 64-Mbit W18/W30
VSS
D[15:0]
S-VCC/P-VCC P-CS#/S-CS1# S-CS2 R-OE#
RAM Die 4-, 8-, 16-Mbit SRAM or 16- or 32-Mbit PSRAM
R-WE# P-MODE R-UB# R-LB#
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
2.2
Flash Memory Map and Partitioning
Consult the latest Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and the Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702), for individual flash die memory map and partitioning information. Table 1 and Table 2 show memory map and partitioning information for dual-flash memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured as a bottom boot while Flash Die #2 (with F2-CE# as its Chip Select) is configured as top boot.
Table 1.
64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning
Partitioning Block Size (KW) Block # Address Range
Parameter Partition Flash Die #2 (32-Mbit)
Partition 0 Partition 1
4 32 32 32 32 32
63-70 56-62 48-55 40-47 32-39 0-31
1F8000-1FFFFF 1C0000-1F7FFF 180000-1BFFFF 140000-17FFFF 100000-13FFFF 000000-0FFFFF
Main Partitions
Partition 2 Partition 3 Partitions 4-7
Partitions 8-15 Partitions 4-7 Flash Die #1 (64-Mbit) Main Partitions Partition 3 Partition 2 Partition 1 Parameter Partition Partition 0
32 32 32 32 32 32 4
71-134 39-70 31-38 23-30 15-22 8-14 0-7
200000-3FFFFF 100000-1FFFFF 0C0000-0FFFFF 080000-0BFFFF 040000-07FFFF 008000-03FFFF 000000-007FFF
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 2.
64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning
Partitioning Block Size (KW) Block # Address Range
Parameter Partition Top Parameter
Partition 0 Partition 1 Partition 2
4 32 32 32 32 32 32
127-134 120-126 112-119 104-111 96-103 64-95 0-63
3F8000-3FFFFF 3C0000-3F7FFF 380000-3BFFFF 340000-37FFFF 300000-33FFFF 200000-2FFFFF 000000-1FFFFF
Main Partitions
Partition 3 Partitions 4-7 Partitions 8-15
Partitions 8-15 Partitions 4-7 Bottom Parameter Main Partitions Partition 3 Partition 2 Partition 1 Parameter Partition Partition 0
32 32 32 32 32 32 4
71-134 39-70 31-38 23-30 15-22 8-14 0-7
200000-3FFFFF 100000-1FFFFF 0C0000-0FFFFF 080000-0BFFFF 040000-07FFFF 008000-03FFFF 000000-007FFF
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
3.0
Package Information
The following packages are offered with the 32WQ and 64WQ Family: * Figure 2, "Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)" * Figure 3, "Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)"
Figure 2.
Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)
Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
Min 0.0079
Inches Nom
Ma 0.04
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.01 0.39 0.31
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.00 0.05 0.02
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 3.
A1 Index Mark
Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)
S1 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Millimeters Nom Max 1.400 1.070 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
Min 0.0079
Inches Nom
Max 0.0551
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0421 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
4.0
4.1
Ballout and Signal Description
Signal Ballout
Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball matrix) device.
Figure 4.
88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
A
B
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
A2
A7
A25
F-WP#
ADV#
A20
A10
A15
E
F
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
S-CS1#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode/ P-CRE
K
L
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Global Signals De-Populated Balls Flash Specific SRAM/PSRAM Specific Do Not Use
Legend:
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
4.2
Signal Descriptions
Table 3 describes active signals used on the 32WQ and 64WQ W18/W30 SCSP family.
Table 3.
Symbol
Signal Descriptions (Sheet 1 of 2)
Type Name and Function ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are internally latched during write operations. * 4-Mbit: A[17:0] * 8-Mbit: A[18:0]
A[21:0]
Input
* 16-Mbit: A[19:0] * 32-Mbit: A[20:0] * 64-Mbit: A[21:0] A0 is the lowest-order word address. A[25:22] denote high-order addresses reserved for future device densities DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes. FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0]. WAIT is High-Z whenever the flash die is deselected (CE# = V IL). WAIT is not gated by OE#. WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are placed in High-Z. F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash die. SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = V IH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die. PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
D[15:0]
Input/ Output
CLK
Input
ADV#
Input
WAIT
Output
F[3:1]-CE#
Input
S-CS1# S-CS2
Input
P[2:1]-CS#
Input
P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or with a single PSRAM.
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 3.
Symbol
Signal Descriptions (Sheet 2 of 2)
Type Name and Function FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z.
F[2:1]-OE#
Input
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations with only one flash die. RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables the RAM output buffers, and places the RAM outputs in High-Z. R-OE# is only available on SCSP combinations with RAM die.
R-OE#
Input
R-UB# R-LB# F-WE# R-WE#
Input
RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die. FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die. R-WE# is only available on SCSP combinations with RAM die. FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-V PP(VPEN) < VPPLK(VPENLK). Erase/ program operations at invalid F-V PP(VPEN) voltages should not be attempted. Refer to the flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products. PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode. Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. P-Mode is only available on SCSP combinations with PSRAM die. FLASH LOGIC Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and #3. Write operations are inhibited when F-V CC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP combinations with only one flash die.
Input Input
F-WP#
Input
F-RST#
Input
F-VPP F-VPEN
Power
P-MODE
Input
F[2:1]-VCC
Power
S-VCC P-VCC VCCQ VSS RFU DU
Power Power Power Power -- --
SRAM Power Supply: Supplies power to the SRAM die. S-VCC is only available on SCSP combinations with SRAM die. PSRAM Power Supply: Supplies power to the PSRAM die. P-VCC is only available on SCSP combinations with PSRAM die. FLASH OUTPUT-BUFFER Power: Supplies power for the I/O output buffers. Ground: Connect to ground. Do not float any VSS connection. Reserved for Future Use: Reserve for future device functionality/ enhancements. Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
5.0
5.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Table 4.
Absolute Maximum Ratings
Parameter Temperature under Bias Expanded Storage Temperature Voltage On Any Signal (except F[2:1]-VCC, VCCQ, F-VPP, S-VCC and P-VCC) F[2:1]-VCC Voltage 1.8 V I/O VCCQ, S-VCC and P-VCC Voltage F-VPP Voltage ISH Output Short Circuit Current 3.0 V I/O 1.8 V I/O 3.0 V I/O Min -25 -55 -0.2 -0.2 -0.5 -0.2 -0.2 -0.2 - Max +85 +125 +2.45 +3.6 +2.45 +2.45 +3.6 +14.0 100 Unit C C V V V V V V mA 1,2,3 2,3 2,3 1,2,3 2,3 2,3,4,5 6 Notes 7
Notes: 1. 90 nm is only avail with the 1.8 V I/O. 2. All Specified voltages are relative to V SS. Minimum DC voltage is -0.2 V on input/output signals, - 0.2 V on F[2:1]-VCC and F-VPP signals. For 90 nm devices, during transitions, this level may overshoot to -1.5 V for periods < 20 ns, during transitions, may overshoot to F-V CC + 1.5 V for periods < 20 ns. 3. All Specified voltages are relative to V SS. Minimum DC voltage is -0.2 V on input/output signals, - 0.2 V on F[2:1]-VCC and F-VPP signals. For 130 nm devices, during transitions, this level may overshoot to -2 V for periods < 20 ns, during transitions, may overshoot to F-V CC + 2 V for periods < 20 ns. 4. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 5. F-VPP program voltage is normally VPPL. The maximum DC voltage on F-VPP may overshoot to +14 V for periods < 20 ns. F-V PP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 6. Output shorted for no more than one second. No more than one output shorted at a time. 7. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE,
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
5.2
Warning:
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 5.
Operating Conditions
Flash + Flash Min TC F-VCC VCCQ S-VCC P-VCC VPPL VPPH Note: 1. 2. Operating Temperature Flash Supply Voltage Flash I/O Voltage PSRAM and SRAM Supply Voltage 3.0 V I/O 1.8 V I/O -25 1.7 2.2 1.7 0.9 11.4 Max +85 1.95 3.3 1.95 1.95 12.6 Flash + SRAM Min -25 1.7 2.2 1.7 0.9 11.4 Max +85 1.95 3.3 1.95 1.95 12.6 Flash + PSRAM Min -25 1.7 2.7 1.8 0.9 11.4 Max +85 1.95 3.1 1.95 1.95 12.6 C V V V V V 1 2
Symbol
Parameter
Unit
Notes
Flash Program Logic Level Flash Factory Program Voltage
F-VPP is normally V PPL. F-VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE,.
5.3
Capacitance
NOTICE: Refer to the 1.8-Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) and 1.8-Volt Intel(R) Wireless Flash Memory with 3 Volt I/0 Datasheet (order number 290702) for flash capacitance details. For SCSP products with two flash die, flash capacitances for each of the flash die need to be considered accordingly.
Table 6.
SRAM, PSRAM Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Typ 10 10 Unit pF pF Condition VIN = 0.0 V, Tc = 25 C, f = 1 MHz VOUT = 0.0 V, Tc = 25 C, f = 1 MHz
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
6.0
6.1
Electrical Specifications
DC Characteristics
SRAM and PSRAM DC characteristics are shown in Table 7 and Table 8. Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and the Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for flash DC characteristics.
Table 7.
Parameter S-VCC VDR
SRAM DC Characteristics
1.8 V SRAM Description Voltage Range VCC for Data Retention 4M Operating Current at min cycle time Test Conditions Min 1.7 1.0 - - - - - - - - - - - - S-VCC 0.15 -0.1 S-VCC 0.4 -0.2 - - -0.2 < VIN < S-VCC + 0.2 V -0.2 < VIN < S-VCC + 0.2 V S-VCC = VDR -1 -1 Max 1.95 - 25 35 40 4 6 10 12 20 30 6 10 18 - 0.2 S-VCC+ 0.2 0.4 - - +1 +1 Min 2.2 1.5 - - - - - - - - - - - - S-VCC 0.1 -0.1 S-VCC 0.4 -0.2 - - -1 -1 Max 3.3 - 45 50 55 10 10 15 15 25 45 5 12 15 - 0.1 S-VCC + 0.2 0.6 - - +1 +1 V V V V mA mA A A A A mA mA V V 3.0 V SRAM Unit
ICC
IIO = 0 mA
8M 16M 4M
ICC2
Operating Current at max cycle time (1 s)
IIO = 0 mA S-CS1# S-VCC-0.2V
8M 16M 4M 8M 16M 4M 8M 16M
ISB
Standby Current
or S-CS2 VSS+0.2V Address/Data toggling at minimum cycle time 1.8 V SRAM: S-VCC = 1.0 V 3.0 V SRAM: S-VCC = 1.5 V
IDR
Current in Data Retention mode
VOH VOL VIH VIL IOH IOL *IIL *ILDR
Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Current Output LOW Current Input Leakage Current Input Leakage Current in Data Retention Mode
IOH = -100 A IOL = 100 A, VCCMIN
* Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 8.
Parameter
PSRAM DC Characteristics
1.8 V PSRAM Description Test Conditions Min Max 1.95 - 30 20 35 - 5 - - 100 - Min 2.7 - - - - - - - - - - Max 3.1 30 mA 2 3 2 35 - 45 5 7 7 80 100 85 A 2, 4 mA 2 mA mA V 3.0 V PSRAM Unit Note
VCC
Voltage Range 8M
1.8 - - - - - - - - - -
ICC
Operating Current at min cycle time
16M IIO = 0 mA 16M 32M
ICC2
Operating Current at max cycle time (1 s)
8M IIO = 0 mA P-CS# P-VCC0.2V. All inputs stable (either high or low) 16M 32M 8M 16M 16M
ISB
Standby Current
P-CS# P-VCC0.2V or P-Mode P-VCC0.2V Address/Data toggling at minimum cycle time
32M
-
100
-
100
A
2, 5
Isbd
Deep PowerDown
P-Mode 0.2 V IOH = -0.5 mA IOH = -0.1 mA
16M 32M
- - 0.8P VCC 1.4 - -0.1 0.8P VCC P-VCC 0.3 -0.3 -0.2
- 30 - - 0.2P VCC 0.2 P-VCC + 0.3 P-VCC + 0.2 0.2P VCC 0.4
- - 2.4 P-VCC 0.3 - -0.1 P-VCC 0.3 P-VCC0.4 -0.2 -0.2
10 10 - - 0.4 0.3 P-VCC + 0.2 P-VCC + 0.2 0.5 0.6
A V V V V V V V V
2, 4 4 5 4 5 4 5 4 5
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOL = 1 mA, IOL = 0.1 mA, VCCMin
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 8.
IIL IOL Notes: 1. 2. 3. 4. 5.
PSRAM DC Characteristics
Input Leakage Current Output Leakage Current -0.2 < VIN < P-VCC + 0.2 V -0.2 < VIN < P-VCC + 0.2 V P-VCC = VDR -1 -1 +1 +1 -1 -1 +1 +1 A A 1, 2 1, 2
Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. All currents are in RMS unless noted otherwise. Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0). Applicable to No-P-Mode (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0)
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
7.0
7.1
AC Characteristics
Flash AC Characteristics
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702)
7.2
Table 9.
# R1 R2 R3 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Note: 1. 2. 3. 4.
SRAM AC Characteristics
SRAM AC Characteristics -- Read Operations
Symbol1 tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ Read Cycle Time Address to Output Delay S-CS1# to Output Delay S-CS2 to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay S-CS1# or S-CS2 to Output in Low-Z R-OE# to Output in Low-Z S-CS1# or S-CS2 to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Parameter Min 70 - - - - - 5 0 0 0 0 0 0 Max - 70 70 70 35 70 - - 25 25 - - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1,3,4 1,4 1,2,3,4 1,2,4 1 1,4 1,4
See Figure 5, "AC Waveform SRAM Read Operations" . Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 5.
AC Waveform SRAM Read Operations
Standby
ADDRESSES R3 S-CS1# R6 S-CS2 R7 R-OE# R-WE# R4 R2 DATA R11 R5 R-UB#, R-LB#
R1 Address Stable R8
R9
R10 Valid Data
R12
Table 10.
# W1 W2 W3 W4 W5 W6 W7 W8 W9
SRAM AC Characteristics -- Write Operations
Symbol 1 tWC tAS tWP tDW tAW tCW tDH tWR tBW Write Cycle Time Address Setup to R-WE# (S-CS1#) and R-UB#/R-LB# Low R-WE# (S-CS1#) Pulse Width Data to Write Time Overlap Address Setup to R-WE# (S-CS1#) High S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) High Data Hold from R-WE# (S-CS1#) High Write Recovery R-UB#, R-LB# Setup to R-WE# (S-CS1#) High Parameter Min 70 0 55 30 60 60 0 0 60 Max - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns Notes 1 1,4 1,2,3 1 1 1 1 1,5 1
Notes: 1. See Figure 6, "AC Waveform SRAM Write Operations" . 2. A write occurs during the overlap (tWP ) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and RWE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#. 3. tWP is measured from S-CS1# low to the end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or R-WE# goes high.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 6.
AC Waveform SRAM Write Operations
Standby
ADDRESSES
W1 Address Stabl e W6 W8
S-CS1# S-CS2 R-OE# W3 W5 R-WE# W4 DATA W2 R-UB#, R-LB# W9 Data In W7
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
7.3
Table 11.
# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PR1 PR2 Note: 1. 2. 3. 4. 5.
PSRAM AC Characteristics
PSRAM AC Characteristics (85ns or 88ns Initial Access) -- Read Operations
1.8 V Symbol tRC tAA tCO tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ tPC tPA Parameter5 Min Read Cycle Time Address to Output Delay P-CS# to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay P-CS# to Output in Low-Z R-OE# to Output in Low-Z P-CS# to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, P-CS# or ROE# change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Page Cycle Time Page Access Time 88 - - - - 10 5 - - 5 5 - 30 - Max 4,000 88 88 65 88 - - 25 25 - - 25 - 30 Min 85 - - - - 10 0 0 0 0 0 0 40 - Max 4,000 85 85 40 85 - - 25 25 - - 25 - 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 4 4 1,2 2 1,2,3 2,3 3.0 V Unit Notes
At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested. Timings of tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM. Applicable to parts with 85ns or 88ns initial access time: (38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0, 28F2240WWYxQ0).
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 12.
#
PSRAM AC Characteristics (70ns Initial Access)-- Read Operations
1.8 V Symbol1 Parameter7 Min 70 Max 15000 8000 70 70 45 70 - - 25 25 - - 25 - 25 8,000 Min 70 - - - - - 5 0 0 0 0 0 0 25 - ns Max 15000 ns 70 Address to Output Delay P-CS# to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay P-CS# to Output in Low-Z R-OE# to Output in Low-Z P-CS# to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, P-CS# or ROE# change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Page Cycle Time Page Access Time CE# low-time restriction - - - - 5 0 0 0 0 0 0 25 - - - 70 70 45 70 - - 25 25 - - 25 - 25 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 3, 4 4 3 2 3.0 V Unit Notes
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PR1 PR2
tRC tAA tCO tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ tPC tPA tCEL
Read Cycle Time
Note: 1. 2. 3. 4. 5. 6. 7.
See Figure 7, "AC Waveform of PSRAM Read Operations" on page 27 and Figure 8, "AC Waveform of PSRAM 4-Word Page Read Operation" on page 27 Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. Parts 38F1030W0YxQF & 38F2030W0YxQF do not support page mode, so this spec will not apply to them CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns Applicable to 70ns initial access P-SRAM's (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2)
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 13.
#
PSRAM AC Characteristics--Write Operations
1.8 V Symbol1 Parameter7 Min Max 8000 - - - - - - - - 8,000 - Min 70 0 55 35 60 60 0 0 60 - - Max - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns 7,8 8 5 4 2,3 3.0 V Unit Notes
W1 W2 W3 W4 W5 W6 W7 W8 W9
tWC tAS tWP tDW tAW tCW tDH tWR tBW tCEL
Write Cycle Time Address Setup to R-WE# (P-CS#) and R-UB#, R-LB# going low R-WE#(P-CS#) Pulse Width Data to Write Time Overlap Address Setup to R-WE# (P-CS#) Going High P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High Data Hold from R-WE# (P-CS#) High Write Recovery R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High P-CE# low-time restriction Write High Pulse Width
70 0 55 35 60 60 0 0 60 - 10
W10
tWPH
Notes: 1. See Figure 9, "AC Waveform PSRAM Write Operation" . 2. A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE# goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high. 3. tWP is measured from P-CS# going low to end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE# going high. 6. W3 is 70 ns for continuous write operations over 50 times. 7. P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 8. Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF 9. Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 7.
AC Waveform of PSRAM Read Operations
R1 R2
ADDRESSES R3 P-CS# R5 R-UB#, R-LB# R4 R-OE# R7 R11 R6 DAT A Valid Data R10 R9 R12 R8
Figure 8.
AC Waveform of PSRAM 4-Word Page Read Operation
R1 R2
A[Max:2]
Vali d Address PR1 Valid Address
A[1:0]
Valid Address R3
Valid Address
Valid Address R8
P-CS# R4 R-OE# R7 R6 DATA PR2 Vali d Data Vali d Data Vali d Data Vali d Data R9
Note:
Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns) 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. Not applicable to 8-Mbit PSRAM.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 9.
AC Waveform PSRAM Write Operation
W1 W2
ADDRESSES W6 P-CS# W9 R-UB#, R-LB# W8 W3 W5 R-WE# W4 DAT A Data In W7
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Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
7.4
Figure 10.
Device AC Test Conditions
Transient Input/Output Reference Waveform
VCCQ , P-VCC
Input
0V
Note:
VCCQ /2, P-VCC/2
Test Points
VCCQ /2, P-VCC/2
Output
AC test inputs are driven to VCCQ, P-VCC for logic "1" and 0.0 V for logic "0". input/output timing begins/ ends at VCCQ/2, P-VCC /2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at VCC = VCCMin.
Figure 11.
Transient Equivalent Testing Load Circuit
I/O Output
Z O = 50 Ohms
50 Ohms
C L = 30 pf
P-VCC /2 = VCCQ /2
Notes: 1. Test configuration component value for worst case specification conditions. 2. CL includes jig capacitance.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
8.0
Flash Power Consumption
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
9.0
9.1
Device Operation
Bus Operations
Bus operations for the W18/W30 SCSP family involve the following chip enable and output enable signals, respectively:
* F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2 * F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2
All other control signals are shared between the two flash die. Table 14 to Table 16 explain the bus operations of products across this SCSP family. Refer to the W18/W30 discrete datasheets (order numbers 290701 and 290702) for single flash die SCSP bus operations. Table 14.
Device
Flash-Only Bus Operations
F-RST# F1-OE# F2-OE# F1-CE# F2-CE# D[15:0] F-WE# F-VPP Notes 2, 3, 4 1, 3, 4, 5 3, 4, 6 4 4 4 ADV# WAIT
Mode
Sync Array Read All Async / Sync Non-Array Read Flash Die#1 Write Output Disable Standby Reset
H
L
L
H
L
X
Active
H
X
Flash DOUT Flash DOUT Flash DIN Flash High-Z Flash High-Z Flash High-Z
H
L
L
H
X
X VPPL or VPPH X X X
Asserted
H
X
H H H L
L L H X
H H X X
L H X X
X X X X
Asserted Active High-Z High-Z
H X X X
X X X X
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
F-RST#
F1-OE#
F2-OE#
F1-CE#
F2-CE#
Device
D[15:0]
F-WE#
F-VPP
Mode
Sync Array Read All Async / Sync Non-Array Read Flash Die#2 Write Output Disable Standby Reset
H
H
X
H
L
X
Active
L
L
Flash DOUT Flash DOUT Flash DIN Flash High-Z Flash High-Z Flash High-Z
2, 3, 4
H
H
X
H
X
X VPPL or VPPH X X X
Asserted
L
L
1, 3, 4, 5
H H H L
H X X X
X X X X
L H X X
X X X X
Asserted Active High-Z High-Z
L L H X
H H X X
3, 4, 6 4 4 4
Notes: 1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. See Section 9.2, "Flash Command Definitions" on page 34 for details regarding flash selection overlap. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30 datasheet (order number 290701 and 29702) for further information regarding WAIT Signal. 3. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 4. L means VIL while H means VIH. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to W18/W30 datasheet for valid DIN during flash writes.
Table 15.
Device
Flash + SRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# F-RST# S-CS1# D[15:0] R-UB#, R-LB# R-WE# F-WE# R-OE# F-VPP S-CS2 Notes 1, 2, 3, 5 1, 2, 3, 5, 6 3, 7 5 5 5 ADV# WAIT
Mode
Sync Array Read All Async/ Sync Non-array Read Write Output Disable Standby Reset
H
L
L
H
L
X
Active
Flash DOUT SRAM must be in High-Z Flash DOUT Flash DIN Flash High-Z Any SRAM mode allowed Flash High-Z Flash High-Z
Flash Die(#1 or #2)
H
L
L
H
X
X VPPL or VPPH X X X
Asserted
H
L
H
L
L
Asserted
H H L
L H X
H X X
H X X
X X X
Active High-Z High-Z
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Datasheet
Notes
ADV#
WAIT
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 15.
Device
Flash + SRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# F-RST# S-CS1# D[15:0] R-UB#, R-LB# R-WE# F-WE# R-OE# F-VPP S-CS2 Notes 1, 4, 8, 2 4, 5, 8, 2 5, 2 5, 8, 2 9, 2 1, 2, 3, 4, 6 1, 2, 3, 4, 6, 7 3, 4, 6, 8 6 6 6 Notes ADV# WAIT
Mode
Read Flash must be in High-Z Write SRAM Output Disable Standby Data Retention Any flash mode allowed
L L L H X
H H H X
L X H X
H L H X
L L X X
SRAM DOUT SRAM DIN SRAM High-Z SRAM High-Z SRAM High-Z
L Same as SRAM standby
Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will override F-WE#. 4. For SRAM, R-OE# and R-WE# should never be asserted simultaneously. 5. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 6. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 7. Refer to W18 and W30 datasheet for valid DIN during flash writes. 8. The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2. 9. The SRAM can be placed into data retention mode by lowering S-VCC to the V DR limit when in standby mode.
Table 16.
Device
Flash + PSRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# P-Mode F-RST# D[15:0] Flash DOUT Flash DOUT Flash DIN Flash High-Z Any PSRAM mode allowed Flash High-Z Flash High-Z R-UB#, R-LB# R-WE# F-WE# R-OE# P-CS# F-VPP ADV# WAIT Active Asserted
Mode
Sync Array Read All Async/ Sync Non-array Read Write Output Disable Standby Reset
H
L
L
H
L
X
Flash Die(#1 or #2)
H
L
L
H
X
X
PSRAM must be in High-Z
H
L
H
L
X
VPPL or VPPH X X X
Asserted
H H L
L H X
H X X
H X X
X X X
Active High-Z High-Z
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 16.
Device
Flash + PSRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# P-Mode F-RST# D[15:0] R-UB#, R-LB# R-WE# F-WE# R-OE# F-VPP P-CS# Notes 1, 5, 2 5, 2 6, 2 6, 2 6, 9, 2 ADV# WAIT
Mode
Read Flash#1 and #2 must be in High-Z Write PSRAM Output Disable Standby Deep PowerDown
L
H
L
H
L
PSRAM DOUT PSRAM DIN PSRAM High-Z PSRAM High-Z PSRAM High-Z
L
H
H
L
L
L
H
H
H
X
Any flash mode allowed
H
H
X
X
X
H
L
X
X
X
Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2. 4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]OE# will override F-WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W30/W18 datasheet for Valid DIN during flash writes. 9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE.
9.2
Flash Command Definitions
Refer to the discrete datasheets, Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash command definitions.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
10.0
Flash Read Operations
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
Datasheet
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11.0
Flash Program Operations
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
12.0
Flash Erase Operations
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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13.0
Flash Security Modes
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
14.0
Flash Read Configuration Register
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations.
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
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15.0
15.1
SRAM Operations
Power-up Sequence and Initialization
The SRAM functionality and reliability are independent of the power-up sequence and power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate is possible under use conditions. SRAM reliability is also independent of the power-down sequence and power-down slew rate of the core S-VCC.
15.2
Table 17.
Symbol tSDR tRDR Note: 1.
Data Retention Mode
SRAM Data Retention Operation
Parameter Data Retention Set-up Time Data Retention Recovery Time Min 0 tRC Max - - Unit ns ns 1 Notes
tRC is defined in Table 7.2, "SRAM AC Characteristics" on page 21.
Figure 12.
SRAM Data Retention Operation Waveform--S-CS1# Controlled
tSDR S-VCC S-VCCmin Data Retention Mode tRDR
S-VIHmin
VDR S-CS1# VSS
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 13.
SRAM Data Retention Operation Waveform--S-CS2 Controlled
tSDR S-VCC S-CS2 S-VCCMIN Data Retention Mode tRDR
VDR
VILMAX VSS
Datasheet
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
16.0
16.1
PSRAM Operations
Power-Up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up sequence and slew rate of the core P-VCC. Any power-up sequence and slew rate is possible under use conditions. PSRAM reliability are also independent of the power-down sequence and slew rate of the core P-VCC. The following power-up sequence and register setting should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 14. Following power application, make P-Mode high after fixing P-Mode to a low level for a period of tI1. Make P-CS# high before making P-Mode high. P-CS# and P-Mode are fixed to a high level for period of tI3.
Figure 14.
Timing Waveform for Power-Up Sequence
Register Setting Power Up P-VCC tI2 P-CS# tI1 P-MODE tI3
Table 18.
Power-Up Sequence Specifications
Parameter tI1 tI2 tI3 Description Power application with P-Mode held low P-CS# high to P-Mode high P-Mode high to P-CS# low Min 50 10 500 Max Unit s ns s Notes 1,2,3
-- -- --
Notes: 1. Toggle P-Mode to low when starting the power-up sequence. 2. tI1 is specified from when the power supply voltage reaches VCCMIN. 3. Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, and 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE line items. Valid PSRAM operations for these line items can begin 200 s after PVcc has reached P-Vcc min.
16.1.1
16Mbit PSRAM Power-Up Sequence (Non-Page Mode) For the non-page mode PSRAM (part's RD38F1030W0YQF, PF38F1030W0YQF, RD38F2030W0YQF, PF38F2030W0YQF) the PSRAM functionality and reliability must be independent of the power-up sequence and power-up slew rate of the core Vcc and the I/O Vcc
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
(Vccq.) Any power-up sequence and power-up slew rate is possible under use conditions. PSRAM reliability must also be independent of the power-down sequence and power-down slew rate of the core Vcc and the I/O Vcc (Vccq.) Once power supply voltages have reached the minimum spec value of 1.7V (or higher), CE# must be maintained high for minimum 200us prior to commencing valid PSRAM operation.
16.2
Caution:
Standby Mode/ Deep Power-Down Mode
All line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Data is lost during deep power-down mode as shown in the Table below. Wake-up from deep power-down mode involves the same initialization sequence as discussed in Section 16.1, "PowerUp Sequence and Initialization" on page 42.
Mode Standby Deep Power-Down Memory Cell Data Valid Invalid Delay time to go Active 0 ns Start-Up Sequence
Figure 15.
Timing Waveform for Entering Deep Power-Down Mode
1 us P-MODE P-CS# Suspend Mode Device Mode Deep Power Down Mode
16.3
Caution:
PSRAM Special Read and Write Constraints
This section will not apply to line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). PSRAM Special Read Constraints
Description Cannot have sub tRC address toggle for more than 4 s in active mode. Need either a read operation or P-CS# high for tRC in that time frame P-CS# high level pulse width Min N/A 10 Max N/A - Unit - ns 1 Notes
Table 19.
Datasheet
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Table 19.
PSRAM Special Read Constraints
R-UB#/R-LB# high level pulse width R-OE# high level pulse width in active mode (P-CS# low) P-CS# low to R-OE# low Address Skew time (unstable address with P-CS# low) 10 10 - - - 10,000 10,000 10 ns ns ns ns 2 1
Notes: 1. Toggling of these control signals is not necessary during address controlled read operations. 2. Address skew time (tSKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, t SKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined.
Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high.
Table 20.
PSRAM Special Write Constraints
Description Need either R-WE# high or P-CS# high for at least tWC time, for every 4us window during write operations. R-OE# high to R-WE# low in active mode (P-CS# low) R-WE# high to R-OE# low in active mode (P-CS# low) Address Skew time (unstable address with P-CS# low) Note: 1. Min N/A 0 10 - Max N/A 10,000 10,000 10 Unit - ns ns ns 1 Notes
Address skew time (tSKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined. Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Appendix A Write State Machine
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details.
Datasheet
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Appendix B Common Flash Interface
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the CFI details.
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Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Appendix C Flash Flowcharts
Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details.
Datasheet
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Appendix D Additional Information
:
Order Number 290701 290702 251216
Document Intel(R) Wireless Flash Memory (W18) Datasheet Intel(R) Wireless Flash Memory with 3 Volt I/O (W30) Datasheet 64-Mbit 1.8 Volt Intel(R) Wireless Flash Memory SCSP Family Application Note
Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. For the most current information on Intel (R) Flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash.
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Appendix E Ordering Information
Figure 16 shows the decoder for products in this SCSP family with both flash and RAM. Figure 17 shows the decoder for products in this SCSP family with flash die only (no RAM). Table 23, "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM)" on page 52 lists available product combinations. Figure 16. Decoder for Flash + RAM SCSP Family Devices
Flash #1 Family
Flash #1
Flash #2
RAM #1
RD3 8 F 2 0 3 0W0 ZBQ0
RAM #2
Flash #2 Family
Packa ge
R D = S CS P P F = P b-free SC SP
Device D etails
0-9, A-D = 1 st Generation, 130 nm E-R = 2 nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O )
Produc t Line D esignator
38F = F lash & RA M Stack D evice
S-Z = 3 rd Generation, TB D
Pinout Indica tor
Q = Q UA D+ ballout
Flash Dens ity
2 = 64-M bit 1 = 32-M bit 0 = N o die
Param eter Loc ation
B = Bottom P aram eter T = Top P aram eter D = Dual Param eter
RAM Dens ity
4 3 2 1 0 = = = = = 32-M bit 16-M bit 8-M bit 4-M bit N o D ie
Voltage
Y = 1.8 Volt I/O Z = 3 V olt I/O
Produc t Fa m ily
W = Intel(R) W ireless F lash M em ory 0 = N o D ie
Datasheet
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Figure 17.
Decoder for Flash-Only SCSP Family Devices
Flash 1/2 Family Flash 3/4 Family
Flash #1
Flash #2
Flash #3
RD 4 8 F 2 2 0 0W 0 Z DQ0
Flash #4
Device Details Package
RD = SCSP PF = Pb-free SCSP
0-9, A-D = 1stGeneration, 130 nm E-R = 2nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O)
S-Z = 3rd Generation, TBD
Product Line Designator
48F = Flash-only Stack Device
Pinout Indicator
Q = QUAD+ Ballout
Flash Density
2 = 64-Mbit 1 = 32-Mbit 0 = No Die
Parameter Location
D = Dual Parameter T = Top Parameter B = Bottom Parameter
Voltage
Y = 1.8 Volt I/O Z = 3 Volt I/O
Product Family
W = Intel(R) Wireless Flash Memory 0 = No Die
Table 21.
32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)
Package Product Number Size (mm) 32 W30 8 x 10 x 1.2 Type Lead-free Ballout Quad + PF48F1000W0ZTQ0 PF48F1000W0ZBQ0 PF48F2000W0ZTQ0 PF48F2000W0ZBQ0 RD48F2100W0YDQE RD48F2200W0YDQ0
(1,2,3,4,5)
Flash Component
64 W30 64 W18 + 32 W18 64 W18 + 64W18 Notes:
8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2
Lead-free Leaded Leaded
Quad + Quad + Quad +
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Intel(R) Wireless Flash Memory (W18/W30 SCSP)
1. 2. 3. 4. 5.
W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. Parts ending with "QE" are 90 nm Flash devices.
Table 22.
Flash Component
32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + SRAM)
RAM Size in Mbit and Type 4 SRAM Package Product Number(1,2,3,4)
Size in Mbit and Family
Size (mm)
Type
Ballout RD38F2010W0YTQ0 RD38F2010W0YBQ0 RD38F2020W0YTQ0 RD38F2020W0YBQ0 RD38F2030W0YTQ0 RD38F2030W0YBQ0 RD38F2020W0ZTQ0 RD38F2020W0ZBQ0 RD38F2030W0ZTQ0 RD38F2030W0ZBQ0 RD38F2230WWYDQ0 RD38F2230WWZDQ0
8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.4 8 x 10 x 1.4
Leaded Leaded Leaded Leaded Leaded Leaded Leaded
Quad+ Quad+ Quad+ Quad+ Quad+ Quad+ Quad+
64 W18
8 SRAM 16 SRAM 8 SRAM
64 W30 16 SRAM 64 W18 + 64 W18 64 W30 + 64 W30 16 SRAM 16 SRAM
Notes: 1. W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
Datasheet
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Table 23.
32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1 of 2)
RAM Size in Mbit and Type 16 PSRAM Size (mm) Package Product Number
(1,2,3,4,5)
Flash Component Size in Mbit and Family 32 W18
PSRAM used
Ballout
Type PF38F1030W0YTQE PF38F1030W0YBQE RD38F1030W0YTQ2 RD38F1030W0YBQ2 PF38F1030W0YTQ2 PF38F1030W0YBQ2 RD38F1030W0ZTQ0 RD38F1030W0ZBQ0 PF38F1030W0ZTQ0 PF38F1030W0ZBQ0 RD38F2030W0YTQ1 RD38F2030W0YBQ1 PF38F2030W0YTQ1 PF38F2030W0YBQ1 RD38F2030W0YTQE RD38F2030W0YBQE PF38F2030W0YTQE PF38F2030W0YBQE RD38F2030W0YTQ2 RD38F2030W0YBQ2 PF38F2030W0YTQ2 PF38F2030W0YBQ2 RD38F2030W0YTQF RD38F2030W0YBQF PF38F2030W0YTQF PF38F2030W0YBQF RD38F2030W0ZTQ1 RD38F2030W0ZBQ1 RD38F2030W0ZTQ2 RD38F2030W0ZBQ2 PF38F2030W0ZTQ2 PF38F2030W0ZBQ2 RD38F2040W0YTQ0 RD38F2040W0YBQ0 PF38F2040W0YTQ0 PF38F2040W0YBQ0 88 ns, with PMODE pin 70 ns, No PMODE pin 85 ns, with PMODE pin 70 ns, No PMODE pin & Non-Page Mode Support 70 ns, No PMODE pin 70 ns, No PMODE pin 70 ns, No PMODE pin 70 ns, No PMODE pin & Non-Page Mode Support
8 x 10 x 1.2
Quad+
Lead-free Leaded
32 W18
16 PSRAM
8 x 10 x 1.2
Quad+ Lead-free Leaded
32 W30
16 PSRAM
8 x 10 x 1.2
Quad+ Lead-free Leaded
Lead-free 64 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded Lead-free Leaded Lead-free 64 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded Lead-free Leaded
64 W30
16 PSRAM
8 x 10 x 1.2
Quad+
Leaded Lead-free Leaded
64 W18
32 PSRAM
8 x 10 x 1.2
QUAD+ Lead-free
18-Oct-2005 52
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
Table 23.
32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 2 of 2)
RAM Size in Mbit and Type 32 PSRAM 32 PSRAM 32 PSRAM Size (mm) Package Product Number
(1,2,3,4,5)
Flash Component Size in Mbit and Family 64 W30 64 W18 + 64 W18 64 W30 + 64 W30
PSRAM used
Ballout
Type RD38F2040W0ZTQ0 RD38F2040W0ZBQ0 RD38F2240WWYDQ0 (6) RD38F2240WWYDQ1 RD38F2240WWZDQ0 RD38F2240WWZDQ1 85 ns, No PMODE pin 88 ns, with PMODE pin 85 ns, No PMODE pin
8 x 10 x 1.2 8 x 10 x 1.4 8 x 10 x 1.4
QUAD+ QUAD+ QUAD+
Leaded Leaded Leaded
Notes: 1. W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 5. Parts ending with "QE" are 90 nm Flash devices. 6. RD38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production
Datasheet
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
18-Oct-2005 53
Intel(R) Wireless Flash Memory (W18/W30 SCSP)
18-Oct-2005 54
Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010
Datasheet

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